An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors

TitleAn Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors
Publication TypeJournal Article
Year of Publication2015
AuthorsChung, S., J. Kong, and F. Koushanfar
JournalIEEE Transactions on Computers
Volume64
Issue9
Date Published8/2015
Keywords3D microprocessor, last-level cache, leakage energy optimization, narrow-width value, process variation, yield
Abstract

As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die-stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

URLhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977972
DOI10.1109/TC.2014.2378291
AttachmentSize
Cache Architecture.pdf2.11 MB

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